Conventionally, memory devices, including but not limited to dynamic random access memories (DRAMs), static RAMs (SRAMs), and electrically erasable and programmable read only memories (EEPROMs) are manufactured with a certain amount of spare elements (i.e., “redundant” wordlines and/or bitlines) available for use as replacements for defective wordlines and/or bitlines.
Such an arrangement can allow memory devices (e.g., chips) that include defects to be fully functional by replacing defective elements with redundant elements. Such defects can arise due to uncontrollable process variations, as but one example. Once defects are replaced, the resulting memory device can have the appearance of an essentially perfect or fully functional chip to an end customer/user.
As would be understood from the above, redundant elements can also significantly improve the device yield, particularly for a product manufactured during the early stages of process development.
A typical memory device can include one or more array regions, each of which can include memory cells arranged in an array along with wordlines and bitlines connected to such memory cells. In most conventional memory devices, bitlines provide a column-wise access to memory cells while wordlines provide a row-wise access to memory cells.
Currently, memory devices can suffer from a variety of failure types that can be repaired by replacing defective elements with redundant elements. Some of the more classical or common types of failures in DRAM devices include: single cell failures, single bitline or wordline fails, bitline-to-bitline shorts, wordline-to-wordline shorts, and wordline-to-bitline shorts. Of course, other types of memory devices can suffer from such defects as well.
After being replaced, different types of failures can have different effects on the operation of a memory device. For example, after being replaced, defective elements may still draw current during operation resulting in a defect current component to overall current consumption in the device.
Typically, single cell, single bitlines and single wordline fails do not drain current from the chip supply after being replaced due to the more self-contained nature of these defects.
However, the remaining three failure types: bitline-to-bitline shorts, wordline-to-wordline shorts, and wordline-to-bitline shorts, are usually a main defect current contributor to a DRAM or other memory type design. That is, even though a defective element may be replaced in a logical or functional sense, the defective element may still draw supply current after being replaced.
A conventional methodology for limiting current drawn by replaced defective elements utilizing current limiter type devices. One example of such a conventional approach is set forth in FIG. 9.
FIG. 9 is a schematic diagram of a portion of a DRAM device designated by the general reference character 900. Conventional DRAM portion 900 includes a memory cell array section 902, a complementary bitline pair composed of “true” bitline 904-0 and “complement” bitline 904-1, and a number of wordlines 906 (WL<3> TO WL<0>). Also shown are a bitline equalization circuit 908 and a sense amplifier circuit 910.
A bitline equalization circuit 908 can equalize complementary bitline pair (904-0 and 904-1) to an equalization voltage (vbleq) prior to a data sense/write operation. In a data sense/write operation, a sense amplifier circuit 910 can amplify a voltage differential between bitlines (904-0 and 904-1) and thereby sense a stored data value or drive a write data value. In a standby mode of operation, bitlines (904-0 and 904-1) can be maintained at a constant voltage (e.g., vbleq), or may be driven in periodic refresh operations.
If a defect exists within the portion 900, the portion 900 can be replaced by another redundant section (not shown) of the same DRAM device. However, in the event the defect results in a bitline (904-0 or 904-1) being shorted to some other element in the device, a current may be drawn from the equalization voltage source (vbleq).
A conventional approach to limiting the standby current drawn from an equalization voltage source (vbleq) is to include a bitline current limiter device between the bitline equalization circuit 908 and the equalization voltage source (vbleq). Such a device 912 may be designed (e.g., sized) to limit a maximum amount of current that can be drawn.
In many conventional DRAM applications, a relatively high standby current specification exists, so the above described conventional method can be satisfactory. However, in other types of DRAM designs, newer memory generations, and/or memories for particular low power applications, a standby current specification can be relatively low.
One particular application in which a low standby current can be desirable is a pseudo static random access memory (PSRAM) application. A PSRAM typically has a one transistor (1-T) cell configuration. Thus, a 1-T PSRAM is a one-transistor cell DRAM-type memory designed to emulate other types of SRAMs. A key goal of many 1T-PSRAM designs is maintaining low current during standby mode. Unfortunately, the above described conventional current limiting method can result in undesirably low yields in the case of 1-T PSRAMs, as array type defects can result in an overall standby current (Isb2) that exceeds the lower threshold of a standby current specification.
A standby current in a 1-T PSRAM may have several components:
(i) Iref: the current required to maintain data in the storage cell capacitor;
(ii) Icircuit: the current drained from circuits that must remain active during standby mode;
(iii) Idevice: the sub threshold current through all the devices in the design; and
(iv) Idefect: the current due to shorts caused by defects that occur during the processing of the design.
In light of the above, it would be desirable to arrive at some way of reducing the defect current contribution (i.e., Idefect) to overall standby current.